Austin, Texas, United States
TECHNICAL SKILLS: • RTL verification using advanced testbenches built on object-oriented techniques leveraging the power of constrained-random stimulus, coverage-driven tests, and code/functional coverage metrics, and assertion-based verification (SystemVerilog, Synopsys-VMM, specman-e) • Experienced building verification components: injectors, monitors, transactors, scoreboards, assertions • RTL, digital system architecture, design, and simulation using VCS (Verilog, VHDL) • Familiar with Verilog programming language interfaces (PLI, VPI, DPI) • Knowledge of clock-domain crossing techniques and Mentor 0-in CDC analysis tool • Experienced with Serdes PCS functions: symbol locking, 8b10b, character scrambling, PRBS, CRC generation/detection. • Knowledge of serial-link procotols: sRIO-1.3/2.1, DP-1.1/1.2, I2C. • Familiar with floating point (IEEE-754) and fixed-point formats, arithmetic, and ALU design. • Familiar wih UVM verification methodology TOOL SKILLS: • RTL/verification simulation (Synopsys VCS) • Functional failure analysis with Verdi automated debug system • Simulation waveform analysis (DVE, Debussy, Verdi) • RTL linting (leda) • Gate level synthesis (Synopsys Design Compiler) • IC layout, DRC/LVS (Cadence Tools) • Digital/analog designs at transistor level, circuit simulation (Hspice, Spectre) • Familiarity with Field Programmable Gate Arrays (Altera) • Experienced with revision control tools (CVS, SOS) • Skilled with C, C++, perl, TCL, shell-scripting, and makefiles for build management. • Experienced with Matlab and Octave. Specialties: • Functional verification with SystemVerilog and VMM • Digital logic design with Verilog RTL
Co-developed object-oriented verification environment (SV/VMM-TB) and testcases to verify high-speed ethernet physical-layer device.
• Developed object-oriented Bus Functional Model (BFM) for DP-1.1a and DP-1.2 (DisplayPort) protocol stack as a verification IP component (SystemVerilog and Synopsys-VMM). • Developed verification environment and testbench for DP-1.1 (DisplayPort protocol) link-extender (SystemVerilog and Synopsys-V MM). The resulting testbench was coverage-driven, constrained-random, and fully self-checking by utilizing injectors/monitors, scoreboarding, and assertions checkers (SVAs). • Developed custom tools to run regressions, analyze and sort fails, and collect, report, and grade code coverage, functional coverage, and assertion coverage (Perl, C)
• Designed/implemented sRIO-1.3 (serial RapidIO) phy-layer protocol stack for four consecutive packet switches (RTL) • Developed embedded processor for FPGA to test robustness of packet switches to sRIO-protocol violations during device validation (RTL) • Designed/implemented sRIO-2.1 phy-layer protocol stack (including sRIO-Part8 error management extensions) (RTL) • Co-developed verification environment and testbench for sRIO packet-switch designs (specman-e).
Performed custom circuit design for PowerPC Embedded Processor Solutions group consisting of dynamic logic for high-speed arithmetic operations.
• Research in the areas of analog/digital/mixed-mode circuit design applied to the development of an artificial retinal prosthesis. The project is a joint effort between ophthalmologists at Johns Hopkins University and electrical engineers at North Carolina State University. The goal is a chronic retina-prosthesis implant to restore limited vision to sufferers of outer-retinal degeneration caused by Retinitis Pigmentosa and Age-Related Macular degeneration.