Bengaluru, Karnataka, India
A Passionate VLSI Engineer with solid experience in Semiconductor industry. # Experienced in PCIe IP/sub-system Verification|| [PCIe] # Experience in SOC verification || Ethernet-800G # Strong Command on System Verilog and UVM || AMBA protocols. # Good Knowledge in Linux and GVIM editor. # Knowledge in repository like Github and version management tools DesignSync [DSSC].
Project: IP/Sub-system Verification [PCIe Gen-6 & Gen7 || PIPE ] — Present work is on SOC level , where two controllers are integrated, will work with 2 controllers back to back connected ,instead of using VIP, we are configuring one controller as RC and other as EP. -- Worked on IP level Verification [PHY, DL,TL,SERDES] Role/responsibilities: # Worked on VIP integration || synopsis VIP || VIP-DUT connection || Dual mode [RP/EP]. # Developing functional testcases to verify features of PCIe [Enumeration (configuring Bar's),Loopback,L0p,Malformed/Poisoned TLP, Lane Margining, Ingress & Egress data transfer]. # Developing regression suites and Owning regression [reporting failures to Team ] # Worked on Code coverage || Functional Coverage [VIP mode] # Debugging functional tests failures with dump in VERDI tool, with reference of transaction log, symbol log, sim log.
Project: SOC Verification [Ethernet-800G || PCS ] -- Worked on SOC level Verification [where Ip's like PMRO, VTMON, PCS, MAX2Phy, Serdes etc.. are involved] Role/responsibilities: # Developed register access testcases for all IP's through AHB,MDIO,TAP & SBUS interface. # Worked on VCF connectivity . # Debugging functional tests failures.
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Assisted in food preparation and kitchen operations for weddings and large-scale events. * Supported chefs in maintaining food quality, hygiene, and timely service. * Coordinated with team members to manage high-volume catering activities. * Developed teamwork, time management, and customer service skills.