Penang, Malaysia
Successfully managed several Soft IP cluster teams, encompassing SATA controllers, Fuse Controllers, Digital Random Number Generators (DRNG) and platform essential IPs (SMBus, RTC, Interrupt controller) for deployment to Intel SOCs and Chipset product development teams. Responsibilities involved customer engagements at the early phase of IP exploration, through to managing IP feature definitions/enhancements with customers and leading IP teams towards IP development and deployment to customers in timely manner and quality.
Responsible for performing power modeling and estimation for Intel Chipset as well as researching low power techniques for adoption to enable Intel Chipsets to meet their idle and TDP power targets. CS also engaged in development with packaging and power delivery engineers to ensure robust power delivery solution for Intel Chipset.
Wide spread experience in the area of logic design, pre-silicon verification, synthesis and timing closure covering designs such as AC'97 audio controller, Intel Hublink and chipset survivability feature.