Hillsboro, Oregon, United States
Experienced Executive / Senior Manager & Technical Leader who has led all phases of the Silicon Integrated Circuit manufacturing life cycle ( 0.8um - 1nm): technology feature definition, DR and PDK development, DTCO / DFM optimization, process-device development, product-process development, reliability improvement, yield-performance co-optimization, process-product-certification, volume yield ramp, fab process transfer and matching, Greenfield factory hiring, startup, high volume manufacturing ramp, and cost reduction, for 10+ generations of CPUs, SoCs integrated circuits and memory ( DRAM / NOR Flash ) products at best in class metrics.
General Manager of YIDDMA responsible for Intel Logic Technology Development Yield, Sort/Test, MIE, Device, Defect, Metrology-FA/FI, External Engagements Analytics
Technical Assistant to the Corporate VP and Co-General Manager of Logic Technology Development
Director for Fab21 E1 Division responsible for Integration, Device/WAT, Yield, Fab Customer Interface, YED ( Yield Excellence Department) - Fab Defect Metrology Departments for N4. The team supported HVM NTO, process improvement / development and manufacturing in Tainan F18 N5 and N4 for ~18 months.
Lead integration technologist for internal roadmap tool feature definition, integrated process development, and customer demo for an advanced new cluster tool application enabling continued Moore’s Law scaling!
Led a team of 14 consultants and analysts in driving a client's successful accelerated development of IP verification, DTCO, Process Yield & Performance for N and N+1 logic process
Led the development, process certification, yield ramp, and transfer of SoC derivative and logic shrink for 90nm, 65nm, 32nm, 22nm, 14nm process nodes, including 22FFL and 22nm eDRAM. Co-manager of the D1C Integration, Device, Yield, Product, Defect Metrology, FA, and Q&R departments.
Led the Integration, Product, Device, Yield, Defect Metrology, Q&R, and Labs Departments in the mother fab seeding, transfer, ramp, and volume production of 130nm Logic and SoC products.
Led the FEOL Integration team in the ramp and manufacturing of 180nm Logic CPUs