Santa Clara, California, United States
Driven by innovation and problem-solving, I am a Post Silicon Validation Engineer currently working at NVIDIA, specializing in PCIe High-Speed I/O bring-up, silicon validation, and system debug on next-generation GPUs/SoCs. My work involves board bring-up, link stability validation, and silicon-level characterization using oscilloscopes, BERTs, and Python-based automation. Previously, as an Embedded Development Engineer at Synopsys, I contributed to the CAN Bus Test Suite, developing embedded software modules and validating DFT features using ATPG tools. I worked on firmware development, communication protocol debugging, and real-time testing for automotive systems. Before that, as a Product Development Engineer (PDE) at Intel, I was part of the post-silicon DFT and yield improvement team for Intel’s flagship Ponte Vecchio (PVC) Xe-HPC GPU. I owned test modules, optimized test programs on ATE systems, and performed silicon debug and data analytics to identify failures and improve overall yield. With a Master’s in Electrical Engineering, my expertise spans: • Post-Silicon Validation (PCIe/HSIO, Silicon Bring-Up, Lab Debug) • RTL Design & DFT (Scan, ATPG, JTAG/Boundary Scan) • Embedded Systems (Microcontrollers, Firmware, Protocol Debug) • Analog & Digital Circuit Design and Simulation • Python automation and data analysis I thrive in lab environments — bringing up chips, validating silicon, debugging complex failures across HW/SW boundaries, and turning early silicon into production-ready hardware. Passionate about next-gen compute, semiconductors, and high-speed interfaces, I aim to continue driving innovation in silicon design and validation.
Supporting PCIe High-Speed I/O (HSIO) post-silicon validation for NVIDIA’s next-generation GPU/SoC platforms. • Working on PCIe link bring-up, lane training, speed negotiation (Gen4/Gen5/Gen6), and link stability testing. • Executing validation test plans, capturing logs, and monitoring link performance using oscilloscope, BERT, PCIe analyzers, and protocol debug tools. • Collaborating with senior engineers to triage issues, document findings, and track fixes through Jira/bug tracking systems. • Running predefined scripts and automation frameworks (Python-based) to collect hardware logs and performance data. • Assisting in setup and configuration of silicon boards, firmware flashing, and power cycle test execution. Focus areas: PCIe bring-up, signal integrity (SI), link reliability, post-silicon debug, Python automation.
Employed by L&T Technology Services, deployed at NVIDIA as a Post Silicon Validation Engineer focusing on PCIe HSIO validation.
• As a Embedded development engineer, I have developed and maintained software solutions for embedded systems, focusing on scan and ATPG-based module validation to ensure testability and reliability in complex integrated circuits • Worked extensively with Automatic Test Pattern Generation (ATPG) tools and methodologies to improve fault detection, diagnosis, and validation efficiency for embedded systems and integrated circuit designs. Optimized ATPG algorithms to generate high-quality test patterns, contributing to the successful validation of SoCs through effective DFT (Design for Test) methodologies. • Focused on implementing DFT strategies and ATPG-based verification for embedded systems, working to integrate testing solutions seamlessly with RTL2GDSII design flows. • Implemented CI/CD pipelines using Jenkins, automating processes to reduce release cycle time by 30%, improving the efficiency of software development and testing, and aligning with industry best practices for continuous integration. • Facilitated Agile ceremonies such as PI planning, sprint reviews, and retrospectives, resulting in a 20% increase in team productivity and better alignment of development and verification teams. • Collaborated with cross-functional teams to integrate the CAN-Bus Test Suite into existing development workflows, reducing manual testing efforts by 40% and accelerating product release cycles. • Demonstrated expertise in CANalyzer for communication testing and diagnostics, JIRA for project and task management, and OTA (Over-The-Air) software solutions for efficient updates and system management. • Gained hands-on experience in DFT insertion, multi-mode timing constraints, and verification flows, with a strong focus on timing optimization and closure for integrated circuits. Contributed to the integration of ASIC components, including power distribution, signal planning, I/O integration, and validation of hard IPs, in alignment with physical design and ASIC integration flows.
• As a Product development Engineer (PDE) the roles ranges from validation of scan content, understanding its architecture, applying Design for test (DFT) techniques to identify and provide solutions for design debugs • As a part of the validation process, the tasks include building modules for test program generation, testing the SoC on Lab testers with different parameters, debugging and data analysis for overall yield improvement. • My skill matrix includes me working with Intel specific tools such as TPIE for module built, AQUA for data analysis and an allocated course work for various tester activities. • Have been a part of intel's product "Ponte Vecchio (PVC) Xe-HPC GPU" as a module owner, working towards building and validating scan module using ATPG, At-Speed methodologies.
• Worked as a Graduate, Teaching and Research Assistant for the course VLSI Design and Introduction to Microprocessor under Professor Dr. Xingguo Xiong • Held tutorial sessions in PSPICE, Layout Editor, Model-sim (Verilog and VHDL), TASM, DOS. • Documented attendance and completed assignments to maintain full class and student records. Maintain atmosphere of academic learning and advancement to facilitate learning and development of critical thinking skills.