Stanford, California, United States
Managed RTL implementation of power management blocks and NoC connection optimizations.
Researched optimizations for memory-compute interconnect structures on 3D chips.
Head CA for EE 108: Digital System Design Head CA for ENGR 108: Introduction to Matrix Methods Managed all logistical aspects of courses, including office hours, review sessions, assignments, and grading. Taught fundamental digital design topics, including coding and debugging RTL, combinational/sequential logic design, static timing analysis, metastability. Taught fundamental linear algebra topics, including matrix theory and least squares regression/application.
Augmented chemical sensor boards with data-logging functionality used in debug. Debugged PID control system for voltage management.