Carlsbad, California, United States
Detailed design of 12-14 Bit, 50-100MSPS Pipeline A/D Converters Detailed design of 12 bit 400MSPS Current Mode D/A Converters Developed as IP blocks for a proprietary octal AFE IC product and contract customers Process technologies: silicon proven in 0.18u Jazz, 0.18u TSMC, 0.13u UMC, 0.13u Silterra, 0.13u IBM, 0.11u SMIC, 65nM UMC, 65nM Toshiba, 65nM IBM processes Responsible for and performed detailed design, simulation, physical layout, bench test validation, customer support, technical presentation, design reviews and documentation. Managed, directed and performed floorplanning and detailed layout and of the chip level integration of IP block into our own Octal AFE chip as well as customer guidance. Tools used. Cadence Analog Artist, Virtuoso, Spectre, Berkeley DA Analog Fast Spice, Matlab / Simulink, Mentor Calibre
Design and development of 10-12 bit and 80-100MSPS pipeline ADC technology. Design and development of several PLLs and DLLs Process technologies 65nm TSMC, 90nM TSMC