Binoy Balan

SOC Architecture lead at Intel

Bengaluru, Karnataka, India

About

Experience

  • Director of Engineering at Intel Corporation
    Sep 2018 - Present · 7 yrs 10 mos

    SOC Architecture lead for Edge server SoC with integrated AI & Networking offload engines.

  • Principal Engineer/Mgr at Qualcomm
    Oct 2014 - Sep 2018 · 4 yrs

    CPU subsystem Micro-architect of mid/value-tier mobile processor based on ARM CPU. CPU subsystem Verification lead of premium-tier, high-tier, mid-tier and value tier mobile processor

  • Principal Engineer at QLogic
    Jun 2008 - Oct 2014 · 6 yrs 5 mos

    Design Verification of 10G/40G/100G Converged Network Adaptors. Handled verification of Host Queue manager, Egress packet generator, Encryption/Decryption blocks and involved in system level simulation activities. Involved in defining verification methodologies for the team.

  • Sr Verification Engineer at Montalvo Computer Systems
    Feb 2006 - Jun 2008 · 2 yrs 5 mos

    Design Verification of x86 based Microprocessor. Handled verification of instruction cache, fetch, decoder and TLB blocks.

  • Component Design Engineer at Intel
    Jan 2002 - Feb 2006 · 4 yrs 2 mos

    Design verification of Multicore Microprocessor.Involved in verification of blocks handling non-coherent protocols, cluster level verification of cache coherency. Post Silicon validation and System level emulation of Ethernet Switches/routers.