Bin ZHANG

QA Architect | QA Manager | Quality Engineering Leader

Greater Paris Metropolitan Region

About

QA Architect and Quality Engineering leader with 10+ years of experience designing and scaling quality strategies for large, distributed, business-critical platforms. I have led QA through major architectural transformations (monolith → microservices) and, more recently, driven pragmatic adoption of AI tools within QA and development workflows to improve efficiency, coverage, and feedback loops. My background spans enterprise platforms, travel technology, and high-complexity systems, with a focus on automation-first, system-level quality and continuous improvement.

Experience

  • FIS (12 yrs 6 mos)
    • QA Architect
      Mar 2022 - Present · 4 yrs 5 mos

      • Define and own QA architecture and quality strategy across multiple teams • Lead QA during monolith-to-microservices transformation, redefining testing layers and automation approaches • Design automation-first frameworks integrated into CI/CD pipelines • Establish quality gates, coverage metrics, and release confidence for distributed systems • Drive adoption of AI tools in QA and development processes, including: AI-assisted test case generation and maintenance Support for exploratory testing and edge-case identification Developer productivity improvements (test creation, debugging, documentation) Ensure AI usage is pragmatic, controlled, and value-driven, aligned with quality and compliance requirements • Reduce regression and stabilization cycles from weeks to days • Mentor QA engineers and act as quality authority for architectural and delivery decisions

    • Senior QA Analyst
      Jul 2018 - Mar 2022 · 3 yrs 9 mos

    • QA Analyst
      Feb 2014 - Jul 2018 · 4 yrs 6 mos

  • Test Automation Engineering(Contractor) at Amadeus
    Feb 2012 - Feb 2014 · 2 yrs 1 mo

    • Test Framework Development(Selenium) • Test Script Automation & Maintenance • Test Campaign Execution • Quality Improvement Initiatives

  • Software Developper Intern at Areva
    Apr 2011 - Sep 2011 · 6 mos

    Design an automated testing framework for power plant control system.

  • R&D Engineer in FPGA at SAGEMCOM
    Jul 2010 - Jul 2011 · 1 yr 1 mo

    Gap year. R&D Engineer in SAGEMCOM Documentation. PDF processing algorithm.