Greater Southampton Area
I built a CPU from scratch last semester. Not because I had to — because I wanted to understand what really happens between a line of RTL and a chip that works. That curiosity is the thread through everything I've done in digital design. At Sion Semiconductor, I spent six months in a real FPGA design flow - writing RTL in Verilog and SystemVerilog, verifying protocol IPs (SPI, UART, I2C, APB), debugging USB 3.2 Link Layer issues at the waveform level, and writing TCL scripts to automate the flow tasks that slow teams down. It was the first time I owned a design problem end-to-end, and I haven't looked back. My MSc in Microelectronics Systems Design at Southampton has pushed that foundation further. I've: → Built a complete TSMC 0.18µm standard-cell library from scratch — scan-enabled flip-flops, MUXes, adders, tristate buffers — characterised for delay, capacitance, and area → Designed and taped out an 8-bit picoRISC CPU on FPGA, including ALU, register file, custom instruction set, and a real-time Gaussian convolution running on hardware → Authored self-checking SystemVerilog testbenches and traced corner-case failures in Cadence Xcelium / SimVision My toolkit: Verilog · SystemVerilog · Cadence Xcelium · Cadence Virtuoso · ModelSim · Xilinx Vivado · Magic VLSI · TSMC 0.18µm · STA · CDC · Lint · DFT · Low-Power Design · FPGA · TCL I'm based in Southampton, eligible to work in the UK, and open to relocating to Swindon. I'm particularly interested in embedded semiconductor roles where the RTL I write ends up in something real. 📩 Open to opportunities — feel free to connect or message directly.
First industry exposure to a full FPGA design flow — owned RTL coding, protocol IP verification, timing closure, and debug across SPI, UART, I2C, APB, and USB 3.2 Link Layer. Delivered clean, synthesis-ready designs in Verilog on Xilinx FPGAs using Vivado and ISE.
Hands-on VLSI training covering standard-cell library design, DFT, low-power techniques, and protocol IP verification — all grounded in real TSMC 0.18µm CMOS. First exposure to the physical constraints that make RTL decisions matter.