Sunnyvale, California, United States
20+ years semiconductor industry experience in both technical and leadership roles at startups & large companies. 16 successful A0 tapeouts, with 13 major chip families in volume production. Extensive chip-design experience in ML, CPU, and DRAM memory domains. Love working on from-scratch projects, and taking them to fruition. End-to-end IC design experience (from feature definition through volume production), customer support, and firmware development. Experience managing small teams to achieve aggressive design goals.
Member of the architecture team at an AI startup.
Owned, defined, and delivered microarchitecture, logic design, performance, timing, and power optimization for several of the largest units on the TensorCore. Contributed to multiple generations of TPU data center ML inference and training acceleration chips, including v5e, v5p, Trillium, Ironwood, TPU 8i, TPU 8t, and more.
Performance modelling, logic design, and micro-architecture definition of multiple units on two generations of from-scratch mobile ARM processors. These chips were the industry's first multi-threaded ARM processors for mobile phones. First generation has been in volume deployment in smartphones since mid-2018.
Load/Store Unit Architect/Tech Lead on Broadcom's first in-house from-scratch ARMv8 CPU core design. Project objective was a 2.0GHz+, out-of-order, multi-core, AArch32/AArch64, low-power, low-area design to go into Broadcom's set-top box and cable-modem products.
As project/technical manager, led XLP3xx series multi-core, multi-threaded network processor project from feature definition to volume production. Directed activities of 40+ engineers across multiple disciplines. Reported progress to CEO & senior executives. In parallel, also managed and grew central engineering teams such as DFT. NetLogic was acquired by Broadcom.