Paris, Île-de-France, France
Senior software/hardware developer and project lead with a track-record of delivering efficient, effective solutions and mentoring diverse technical teams.
Technical lead of a five-person team across Germany and India on the internal graphics debugger used for internal pre- and post-silicon validation and driver development. Responsible for product definition, feature development and technical mentoring of engineers both within and outside the team. Interface with customers and stakeholders across multiple geos in North America, Europe and India. Developed system routine for user-level OpenCL and SYCL GPU debugging in the oneAPI project. Trace data search and filter project lead, driving a nine-person engineering effort across Germany and Israel. Architected and implemented a high performance search engine in C++ for IA-platform trace data using JIT-compilation to perform a query through millions of records per second.
Technical lead of a five-person team providing Intel's emulation execution tool. Owned back-end infrastructure, including the specification for Netbatch, Intel's internal distributed job system. Transformed Intel's emulation execution tool from a vendor-specific utility to a multi-vendor execution platform for Mentor and Synopsys emulation platforms and HAPS FPGA, enabling Intel to drive a major platform transition with minimal user impact. Integrated emulation model compilation into graphics chipset design's continuous integration environments, significantly increasing model delivery cadence and health.
Delivered weekly RTL models & simplified a complex build flow into a single command for all users. Transitioned simulation toolset to a new python-based environment. Parallelized the internal Verilog stitching tool, accelerating model build time by 5x.