Austin, Texas, United States
Static timing analysis engineer.
As full chip timing owner, I am responsible maintaining full chip timing infrastructure and releasing timing models. Work closely with physical designers, clock, circuit, design automation, RTL and SoC teams for timing closure. Responsible for rolling down budgeted timing constraints for partitions and closely collaborate with designers to resolve any issues related to timing constraints in partition synthesis, PNR, STA flows. Automated flow to visualize timing paths and highlight potential issue(s) for quick debug and triage. Maintain scripts to generate TNS/WNS/NVP indicators to keep track of the timing convergence progress. Experience with UPF format and closing timing in multiple voltage domain to cover paths in cross voltage scenario. Experience in OCV, AOCV and POCV derating methodology and knowledge of cross talk and noise analysis. Good understating of NLDM, CCST, CCSN and LVF library modeling, types of timing arcs and attributes. As part of CPU IP provider, enabled scaling flow to generate timing collaterals for different PVT corners (other than primary corners) for SoC drops and wrote scripts to check the quality of the timing collaterals. Work with SoC teams to help them seamlessly integrate timing libs in their model and resolving issue(s).
Worked on automating sign off paranoia/quality checks for project tape out using perl and tcl languages at full chip and block level for different verification flows such as timing, formal equivalence checking, assembly, PDS and RV. Triaged reported errors and followed up with stakeholders to get violations either fixed or waived. Optimized scripts for runtime reduction to improve turn around time for full chip assembly/verification flows.
Designed software for intelligent lighting solution. Work on developing hardware and firmware of DALI (Digital Addressable Lighting Interface) controller. Developed JAVA application to merge to photometry files (IES files) and to generate LM79 report. performed electrical test and thermal test on newly developed LED drivers. Maintained test result documentation and released new product documentation. Tested newly developed product in photo-goniometer to generate photometry profile.
Worked with PCB Design unit and Technical Department and conducted a study on different stages of PCB manufacturing process.