Raleigh-Durham-Chapel Hill Area
Experienced engineer with expertise in RTL implementation(SystemVerilog, Verilog, VHDL) and microarchitecture development in the areas of processor memory subsystems, cache coherency, cache pipelines, error correction codes(ECC), and DMA accelerator blocks. Demonstrated ability to meet challenging deadlines with multiple deliverables.
Octeon Fusion baseband processor RTL design ThunderX Arm server processor L3 Cache Unit Owner and Memory Subsystem Design ● Write and maintain microarchitecture documents for L3 unit ● Implement L3 Cache and IO Write Cache Unit(WCU) RTL in Verilog and SystemVerilog ● Analyze architecture proposals and collaborate on solutions ● Define microarchitecture for new features ● Evaluate cache size and SRAM options with physical design team ● Assess new memory subsystem features and size potential impacts ● Conduct high level design reviews for L3 and review interdependent memory subsystem units ● Debug complex memory subsystem bugs and identify fixes ● Coherency
● Cache Subsystem Reliability/Availability/Serviceability(RAS) ● L3 Cache Logic Design ● L4 Cache Logic Design ● Master Inventor ● Memory Control Unit (MCU) Key Cache Logic Design ● Cache Coherency
● Built 4-channel, 4-proccessor A/D converter and capture VME based DSP system with Pentek parts following customer specification. Wrote demonstration embedded code and presented to customer.