Arnaud Epinat

Imaging Hardware Digital Design & Verification

Greater Lyon Area

About

Experienced Hardware Digital Design & Verification Manager with a demonstrated history of working in the semiconductors industry. Strong arts and design professional skilled in Universal Verification Methodology (UVM), SystemVerilog, Application-Specific Integrated Circuits (ASIC), Microelectronics, and Integrated Circuits (IC).

Experience

  • STMicroelectronics (12 yrs 9 mos)
    • Imaging Hardware Digital Verification
      Aug 2020 - Present · 5 yrs 11 mos

    • Imaging Hardware Digital Verification
      Aug 2017 - Jul 2020 · 3 yrs

      Project Leader

    • Imaging Hardware Design Manager
      Oct 2013 - Jul 2017 · 3 yrs 10 mos

      SOC & IP Digital Design

  • ST-Ericsson (Greater Grenoble Metropolitan Area)
    • Imaging Subsystem Hardware Design & Programs Manager
      Jul 2010 - Sep 2013 · 3 yrs 3 mos

    • Imaging Subsystem Hardware Design & Programs
      Feb 2009 - Jun 2010 · 1 yr 5 mos

  • STMicroelectronics (Greater Grenoble Metropolitan Area)
    • Imaging Subsystem Hardware Design & Programs
      Jul 2008 - Feb 2009 · 8 mos

      Wireless Division

    • Application & Technical Support
      Jul 2007 - Jul 2008 · 1 yr 1 mo

      Wireless Division

    • Design/DFT project leader
      Jan 2000 - Jun 2007 · 7 yrs 6 mos

      R&D division