Birmingham, England, United Kingdom
RTL Design Engineer with expertise in digital logic design, Verilog/SystemVerilog. Loves to troubleshoot and debug.
•Fully qualified Retrofit Coordinator (L5) and assessor, working in line with PAS 2035:2019 and TrustMark requirements •Regularly produce and lodge Energy Performance Certificates (EPCs) using RdSAP methodology. •Skilled in creating occupancy assessments and aligning retrofit strategies with occupant behavior and fuel poverty concerns. •Experienced in specifying and coordinating measures including External Wall Insulation (EWI), Cavity Wall Insulation (CWI), Loft and Roof Insulation, Floor Insulation, Efficient Boilers (condensing), Smart Heating Controls (zoning, TRVs, programmers), and with airtightness improvements. •Coordinated and managed domestic retrofit projects from assessment to completion. •Developed Medium-Term Improvement Plans (MTIPs) based on RdSAP and other technical assessments. •Competent in identifying and mitigating moisture risks, ensuring proper ventilation and thermal bridging assessment •Delivered tailored retrofit strategies including fabric-first approach and appropriate ventilation strategies (e.g., MEV, DMEV, trickle vents). •Ensured compliance with TrustMark and other regulatory frameworks. •Experienced in handling compliance and audit requirements from regulatory and certification bodies including IAA, NICEIC, TrustMark, and Elmhurst. •Reviewed Improvement Option Evaluations (IOEs) to recommend suitable energy efficiency measures. •Identified risks and provided risk assessments and mitigation strategies. •Maintained ECO4/GBIS accurate project documentation for compliance and audit purposes. •Experienced in submitting retrofit project documentation and evidence to funders, ensuring compliance with scheme requirements such as ECO4/GBIS. •Ensure that retrofit works are carried out safely, considering both installer and occupant safety during and after installations.
• Designed a router for a Network-on-Chip (NoC) architecture based on the CHI protocol, implementing the XY routing algorithm to transfer packets between SoCs. The router supports multiple channels including snoop, data, snoop response, request, and completion response. It receives packets through various ports (depending on the channel) and routes them either to the Central CCB or neighboring nodes. The NoC was structured using a mesh topology. Proposed the overall architecture and developed the RTL using SystemVerilog, including comprehensive testing through randomization. Performed linting using Cadence tools to ensure code is synthesizable. • Designed a RISC-V32IC 5-stage pipelined processor implementing instruction fetch (IF), decode (ID), execute (EX), memory access (MEM), and write-back (WB) stages. Integrated data forwarding and hazard detection mechanisms to handle instruction formats (R, I, S, B, U, J types) efficiently. The processor also supported the RISC-V Compressed Instruction Set (C extension) enabling 16-bit instruction decoding and execution. RTL was developed using Verilog HDL. Performed physical design analysis, including synthesis, floorplanning, placement, clock tree synthesis, and routing, using the OpenLane flow. • Cache simulator: Determines the AMAT, Hit/Miss rate of different caches on particular traces. • Physical Design: Implemented the PD of RISV-32IC using openLane. • Verification of RAM using layer test bench.
• Contributed to the modernization of the HUD (Head-Up Display) Electronic Unit (HEU) system used in aircraft by re-engineering legacy hardware components into FPGA-based architectures. This involved analyzing and reverse-engineering obsolete or unsupported circuitry for several mission-critical cards, including the Raster Output Card for real-time video stream generation and display, the Graphic Controller Card for rendering and overlaying symbology data, the Cursive Output Card for managing vector display elements and text drawing, and the WFG (Waveform Generator) Interface Card for integration with analog subsystems to generate and control waveform outputs. • Implemented key digital components on FPGA, including a custom 16-bit processor, instruction sequencer, and FIFOs. Conducted functional verification and successfully deployed the design on a Spartan-6 FPGA. Applied timing constraints and optimized physical placement of logic blocks to meet performance and resource utilization goals. • Designed schematics and developed multi-layer PCBs using Altium Designer, ensuring optimal component placement, signal integrity, and manufacturability for high-reliability electronic systems. • Extensive hands-on experience with advanced logic analyzers and oscilloscopes, expertly troubleshooting and debugging complex hardware systems. Hardware debugging involves detailed signal analysis and innovative problem-solving to optimize digital system performance.
Worked at Power Electronics Lab. Worked on the project “GSM Based Energy Meter”. Developed the double layer PCB and did coding in Arduino IDE.