Anuradha Bhari

Member of Technical Staff

San Jose, California, United States

About

Experience in Hardware Architecture, High Speed Board Design, Validation, Debugging and System level interfacing for Networking/Telecom and embedded applications. • • High Speed Board Design, System level design • Signal integrity, timing and power analysis • Component selection, Schematic Capture, BOM generation, PLM • PCB stack-up, layout, component placement and review • Board bring-up, debug, Design validation testing • System thermal testing • Sustaining support and Critical customer support • Work on NPI projects, prototyping • Hardware design re-spin and cost reduction • Proficient with Cadence Orcad and Allegro PCB tools • Knowledge of x86 and MIPS CPU based design • Knowledge of FPGA/CPLD design

Experience

  • Member of Technical Staff at Etched
    Sep 2025 - Present · 11 mos

  • Member of Technical Staff at Enfabrica
    Mar 2025 - Aug 2025 · 6 mos

  • Senior Hardware Engineer at Cisco
    Jun 2024 - Feb 2025 · 9 mos

  • Cruise (Full-time · 3 yrs 3 mos)
    • Staff Electrical Engineer
      Aug 2022 - Jun 2024 · 1 yr 11 mos

    • Senior Hardware Engineer ll
      Apr 2021 - Aug 2022 · 1 yr 5 mos

  • Teledyne LeCroy (Full-time · 3 yrs 8 mos)
    • Staff Hardware Engineer
      Jan 2021 - Mar 2021 · 3 mos

    • Senior Hardware Engineer
      Aug 2017 - Jan 2021 · 3 yrs 6 mos