Zurich, Zurich, Switzerland
Anthony is currently a VLSI design engineer working on front-end design (RTL, synthesis & simulation), as well as on firmware design. Previously he worked as a digital ASIC/FPGA design engineer for various clients at easics. Before that he was a research assistant at ESAT/COSIC, KULeuven, where he focussed on efficient security solutions for embedded designs and obtained his PhD in Electronic Engineering. Specialities: VLSI design (SystemVerilog, UVM, VHDL), software design (C++)
• Design and implementation of FPGA (VHDL) and firmware design (C & C++) for Quantum Computing Control System devices.
• Software architecture and implementation of tooling for HW-based Deep Learning IP and in-house tools (mainly C++). • Project for various industries: European Space Agency, Keysight, Sony, HW TCP/IP stack, Deep Learning accelerator, ... • Design and implementation of hardware architectures for ASIC & FPGA (VHDL), ranging from a few K to >100M gates. • Design and implementation of test environments (SystemVerilog/UVM and SystemC/C++). • Giving training seminars on various aspects of C++.
PhD research on efficient implementations and algorithms for embedded security. Thesis title: "Lightweight PUF-based Key and Random Number Generation” Supervisor: prof. dr. ir. Ingrid Verbauwhede Work on European FP7-funded projects "UNIQUE” and "PUFFIN”. Active involvement in multiple FPGA and embedded microcontroller design projects. Supervision of multiple Master theses, supervision of inverted pendulum robot design project, ... Practical organization of CHES 2012 conference.
Responsible for support & improvement of IT infrastructure and backend for 2000+ students.