Sunnyvale, California, United States
As a Senior Product Development Engineer at Intel Corporation, my focus is on pioneering post silicon debug techniques for next-generation microprocessors. With a Master's Degree in Electrical Engineering from the University of Buffalo, I leverage my expertise in ATPG, silicon debug, and fault isolation to enhance product performance and yield. My role also involves collaborating with optical tool vendors for improvement and leading knowledge-sharing initiatives across different teams and geographies. This contribution not only furthers Intel's product leadership but also reflects my commitment to continuous learning and teamwork within the dynamic semiconductor industry.
Intel Design Engineering Group is a global team responsible for the design, development, validation, and manufacturing of IPs and SOCs. Our mission is to deliver leadership products through groundbreaking innovations. In this new role, regularly communicating with optical tool vendors for improvement steps and future-proofing post silicon debug for upcoming advancements in semiconductor industry. Also, lead the team, by being key contributor in knowledge-sharing across different teams and GEOs, to drive overall improvement in silicon debug. These responsibilities were in addition to the previous roles’ responsibilities. Highlights are: (in addition to previous highlights) - R&D for new tools and technology upgrades to the existing toolset to close forecasted future gaps in the debug toolset for forthcoming technology nodes. - Develop and execute standardized methodology in a dynamic environment and use concepts such as LEAN and 6S to organize and streamline activities
In my role, I worked in Post Silicon Debug team on product readiness and debug activities for Next Generation Microprocessors. Worked closely with debug engineers, circuit design and LYA members to execute testing and obtain data on-die for silicon debug and fault isolation. Highlights are: - Use ATE and FI,FA tools such as Lock-in Thermography, E-beam prober, LVP-Laser Voltage Probing, LADA-Laser Assisted device alteration, IREM- infrared emission microscopy, MicroProbe and ATE tester - Execute die-level testing by using various test patterns to debug circuit defects, marginalities and help improve the overall yield and performance of the products
• Designed Double-sided and Multilayer PCBs, by following Design for Manufacturing (DFM) guidelines, which involved high speed component routing, high voltage/amperage power conditioning, library part creation and maintenance, performing error checks and creating output files such as Gerber and NC Drill files into a complete package to include all PCB data. • Provided complete PCB manufacturing data package to vendors including board panelization and communicating with the vendors for future troubleshooting. • Gained proficiency with Embedded and Model-Based designing, post design processes including MIL, SIL, PIL, and HIL testing and Signal Integrity and Thermal Analysis tools provided by various CAD software. • Conducted global training for Altair PollEx - an EDA simulation tool for PCB viewing and performing verification checks namely DFT, DFF and DFA, analysis like Signal Integrity, Power Integrity and Thermal Analysis and includes Manufacturing suite tools. • Supported external users (customers) with upto 16-layer PCB design, verification and analysis
Experience working in the major departments of Telecom Industry like Data Center, RF dept and field service dept, NAC (Network Access control) dept Supported the deployment and maintenance of e-Node B (ENB) antennas and optical fiber network across ‘PAN India’ Experience in cell-site processes like fiber testing using OTDR, fiber splicing and site testing