San Jose, California, United States
OBJECTIVE: Utilize leadership, engineering, customer relations, and project managment skills in a Product/Test engineering Position. I leverage Semiconducter Product, Test, validation, char, PM, quality, reliability, fab, packaging, data analysis and software design and development experience, along with lab and practical experiences in the ATE, semiconductors, Aerospace and NDT industries to successfully pursue these goals. SKILLS and KEYWORDS: Silicon Development - DFT, DFM, product and test engineering, quality, reliability, fab, packaging, data analysis Chip types - GPUs, CPUs, HPUs, ToF, image sensors, touch sensors, pen sensors, MCUs Management/Leadership - technical leadership (product/test eng), personel management, strategic, vendor (silicon, turn-key, subcons) management, budgeting. ATE systems/SW/Instrumentation/Handlers/Probers/Manipulators- Teradyne J/IP-750, Tiger, Catalyst and A5, Agilent 93000; IG-XL and IMAGE; ICUD, CTO, AWG5000, MODCLK, GIGADIG, AWGLAN, BBAC, VHFDIG; Seiko Epson NS7000; Accretech UF200/300; GPIB/RS232 protocols CMOS Imager & Mixed Signal Device Testing- CCP, CCP2, MIPI, HiSPI, LVDS, I2C, CIF,VGA/1-16 Mpixel sensors, DSLR, Image Analysis algs, DSP, Char Testing (Lag, x-talk, Min-Gain, Response, Dark Current, ADCs etc), JTAG Other- MatLab, JMP, h-spice, p-spice, Electric (IC Layout tool), MS Project, MIPS and DLX Assembly, Altera MaxII+ (PLD), VHDL (FPGA), Motorola CPU12, AutoCAD R13, C++/C (XP, UNIX, Linux), Python, CORBA, DLLs using ATL/COM, VB, PERL scripting, SVN, CVS, Rational Clearcase and Clearquest, CGI, SQL, MSQL, HTML Specialties: Silicon Test Engineering, Subcontractor Vendor Management
I currently manage a team of lead product/test engineers along with leading various chips/projects myself as well. I Have the opportunity to work on custom chips that are go into Microsoft devices: XBOX, Hololens, Surface and IoT, and we closely work with product teams to understand where chip optimization and efforts will have the largest impacts on the success of the product. These chips include GPU/CPU SoCs, HPUs (Holographic Processing Units), touch sensors, pen sensors, 3D ToF image sensors, custom MCUs. The chips are a mix of chips solely developed internally and chips developed thru partnership with major chip developers. The work and responsibility span from business opportunity definition, thru design, first silicon bring up, characterization/validation phases, NPI, mass production support, thru end of life. The group is responsible to lead or support all classical areas of silicon development and manufacturing such as DFT, DFM, validation, characterization, fab, test, quality, reliability, packaging. Key areas of focus are power optimization, performance optimization and quality. In addition, the group is at the forefront of pioneering new methods to support our goals by leveraging product performance and usage data made recently available thru advancements in the cloud and big data.
Position: Sr. Test Engineer- 3D-ToF CMOS Imagers / Subcon Management Duties: Primary Test Engineer resource to handle all test aspects of a new generation 3D Time of Flight CMOS image sensor chip. Tester specification, HW specification, test program design/development, first silicon bring-up, debug and characterization, transfer to mass production, and vendor management are among the tasks performed. •Bring-up and debug of ”first silicon” for our new generation 3D ToF sensor. Focused on validation of features, chip characterization; Delivered initial samples to an aggressive schedule. •Char testing – Plan and develop tests for device characterization (IE: oscillator min/max frequency search, ADC INL/DNL, Memory char, Temporal Noise). •Test flow development – Test program written on Teradyne’s IP750 platform. Tests include parametric testing and analysis, digital tests via JTAG, as well as optical testing: (image capturing) and image analysis, utilizing Teradyne’s built-in DSP routines. Flows written for probe production (wafer), final test production (CSP package), as well for a ‘qual read-point flow’. Also assisted with selection of temperature for testing. •Specified, reviewed designs and brought up production dual site-probe card for manufacturing. •On the team who selected both the production probe and final test facilities. Initially brought up these test facilities, correlated/qualified the production flows which include electrical testing, inspection criteria and packing/shipping. •Ongoing product support - Responsible for compliance of test specifications, yield, test time and data analysis (JMP, MatLab, and scripting used for analysis); handling data formats, conversions, and data archiving. •Work on cost reductions – Specifying and experimenting with low cost tester modules, and low cost light source solutions. •Plan for test (DFT, test flow, platforms, capacity plan, etc) for next chip, currently in pre-tape out phase.
Position: Probe/Test Engineer- CMOS Imagers/ ATE development /Subcon Management Duties: Design and develop test programs for CMOS image sensors in IG-XL (Windows systems) for Teradyne IP-750 testers. First Silicon bring up, characterization, ongoing product support and production support. Also, I am tasked to oversee transfer of testing to Subcons based overseas. •First Si Support – Responsible to plan and implement the initial test program and part of the team that evaluates the ”first silicon” of a new device. Tests include parametric testing and analysis as well as optical testing (image capturing) and image analysis. Focus is on quality of algorithms (catching defects and not false fails) as well as minimizing execution time. •Char testing – Plan and develop tests for device characterization (IE: Lag, Min-Gain, X-talk, etc.). •Ongoing product support - Responsible for compliance of test specifications, yield, test time and data analysis (JMP, perl and other tools on UNIX systems); Analyzing/adding coverage for RMAs. •Main engineering contact for selection/bring up/ongoing management of offshore test houses (KYEC is one of them). Also work to enable assembly houses thru setting up both ATE and in-house/low cost equipment, to do package test so as to simplify supply chain and reduce cost. •On multiple project teams mandated to develop and deploy various CMOS imager test equipment (testers, light-sources) as a SW, calibrations, correlations, and review/auditing resource. •Plan, develop and review board design and optical setup and issues (light requirements – halogen/LED, lens modules, diffusers, etc). •Develop test procedures, compile data, and make recommendations for changes required in test equipment, procedures, manufacturing/group processes and data management. •Design, develop, deploy and troubleshoot procedures used by manufacturing and equipment support personnel on the test floor.