Warsaw, Mazowieckie, Poland
I am a results-driven Software Engineer with a passion for designing and scaling distributed systems that operate under high-throughput, mission-critical constraints. My expertise lies in full-cycle engineering, from architecture and implementation to identifying systemic bottlenecks and delivering high-impact performance optimizations. I thrive on translating complex business challenges into robust, resilient, and measurable technical solutions.
• Uplifted core accrual calculation business logic, transforming it into a stateless component, reducing calculation time from 1.5 hours to 4 minutes for whole client universe • Remodeled and unified the client configuration model of accrual platform, streamlining complex configuration traversal logic • Streamlined pre-trade file delivery mechanism with MongoDB and Kafka Streams, reducing delivery time to within 5 minutes of upstream data readiness and eliminating reliance on legacy system • Analyzed and resolved high-impact, time-sensitive client fee discrepancies, managing communication with business stakeholders • Drove platform stability and performance initiatives by identifying common systemic issues, leading the analysis and proposing cost-effective, high-impact solutions
• Cut trading-critical application startup time from 4 hours to 3 minutes by implementing a Kafka Streams-based cache, significantly mitigating business risks associated with outages
• Mentored and supervised second-year undergraduate students in compiler design and development for the Language Processors course • Provided expert guidance on developing a C-to-MIPS compiler in C++ • Coached students on effective compiler debugging techniques and optimal design approaches
• Developed Virtual Prototypes for hardware architecture exploration of components of high-end wireless communication chips • Proposed and developed the Python-based TCL generator using Jinja2 to automate the process of assembling Virtual Prototypes • Integrated cycle-accurate SystemC models of ARM processor and interconnect components into Platform Architect • Documented the Virtual Prototype development flow to serve as a basis for future SCSC projects
• Developed a behavioral SystemC transaction-level model for a MAC unit by translating its SystemVerilog hardware implementation • Gained experience in the industry-standard hardware development flow and presented progress updates, culminating in a final presentation to the management team.