Saratoga, California, United States
With over 33 years working in the computer design industry, I have gone through all phases in micro-Architect definition, logic RTL design implementation, design verification, GLS, debugging, synthesis, timing closure, Formal verification, P&R, power, I/R drop, RV, FP, CTS, and ATPG coverage, schematic capture. Also familiar with CXL/PCIe, AXI4, ACE, APB, USB, DDR, I2C, SPI, and other bus protocols and memory coherence. Worked on the SOC design using the ARM and FlexNoC to build the subsystem up to 9 processors, like the Cortex A53. The Coresight was built with Socrates tool. Built the subsystem design also includes 3 AHB and 2 APB buses to connect to 2 cortex M33 and ADSP (Xtensa) and FlexNoC crossbar. Also use QUARTUS to build example design and IP for the test bench for the SSD Cache design verification. Specialties: Experienced in RTL coding with Verilog; Validatuion in C++, System Verilog, specman elite, UVM and scripting tool in Perl, Tcl, Python. Have gone through the designs in PCIE, FIFO, Arbitor, AMBER, I2C, USB, LRU for the 4-way cache, PostgreSQL Scan including in list, in range, column scan, Postgres, Greenplum, DDR, SSD, SysAD in MIPS and SBus and MBus in SUN Microsystem and also Multiprocessor designs like jaketown (Xeon E5-2600), ivy bridge (i7), ivy town (Xeon E7), Skylake project (28 cores) and now ARM Sub-system and worked through the 65nm, 45nm, 32nm, 22nm, 14nm, and 7nm process technology.
Research in Memory Solution Lab. Done with CMM-H Memory Design verification with SystemVerilog for 30GG/s, 16 slices design. It includes Tiering, Cache GPF, and Cache policy (Prefetch/Evict/Flush/Copy/Copy-B/Func Offload/FW update) design using CXL/PCIe, ARM subsystem and basic offload (grep/scan/ETL). Completed the design verification with SystemVerilog for the type2 with CXL.mem and CPI with the interface channels of m2s request, m2s data response, s2m no data response, and s2m data response. Built UVM test bench from scratch. Done with the design verification of PostgresSQL and Greenplum and Pattern Search SSD and Data compression with prefix, run length, index vector, sparse, in-list, in-range, column scan, and indirect algorithm. Also, data scatter and gather,16B alignment for both read and write with AXI bus protocol. Dedupe engine design for AI memory research with 8 write and 8 read engines, write Coalesce buffer (WCB), parallelism for the AI intelligent data recognition and storage algorithm implemented in memory System and using C++ to build reference model.
Working as Architect to define Viaphy3 subsystem and also involved RTL Design for ViaSat Satellite company, including 9 ARM CPU Cortex A53s, crossbars like CCN-502, NIC-400, with the peripherals like DMA, PCIe, DDR, SerDes, Temp Sensor, LDO, debugger Coresight, memory like OCM, ROM, security like CryptoCell, and other components like GIC-500, ADB-400, with the bus protocols of ACE, AXI 4, CHI, APB, etc. The Coresight and SMC for SRAM are built from Socrates tool, FlexNoC from Arteris tool. Setup test bench and ran VIP CAT and IUS uvm; Also Built the IWB test bench. In Facebook’s Luna project, built Coresight subsystem with 2 M33 cores, FlexNoC, 3 external AHBs, 1 system APB, and 1 external APB buses. Modified the subsystem by replacing the TPIU with SWO port and taking out the funnel logic, etc. Built tests for register access and ADSP access, etc.
IP Architect for the DDR in 7nm with PSM, RTL design like bus expansion, behavioral model for RF blocks, calibration, PSM, delay line, eFuse, and design spec and verification documentations and supervise the design, layout, circuit verification of high-speed DDR/SERDES transceiver elements (IOs, equalizers, high-speed clock distribution (5-20GHz)), and other SerDes/DDR blocks at data rates of 5Gb/s and higher.
Derived GSM (graphic state management unit) for USM and USC graphic state control logic and flow for the primary tree in the GPU design. Developed the primary tree to communicate to the USM and USC with IA and all the shader constructor, VSC (vertex), HSC (hall), TES (Tessellation), DSC (domain), GSC (geometry), and SO (stream out), CCV (clip and cull), SU (setup), RASZ (rasterization and Z), CROP (color), and TB (tile);