Andrew Ding

Asic Engineering

Irvine, California, United States

About

Seeking internships in ASIC Design or Computer Architecture related roles. Ex-SpaceX Starlink Silicon CPU/NoC performance verification engineer, with industry tape-out experience. Current PhD student designing and tape-out of novel Risc-V Vector Processor architectures for ML Inference at the edge. Star Trek enthusiast. Seen every episode on Seinfeld thrice.

Experience

  • RTL Design Engineer at Tenstorrent
    May 2026 - Present · 2 mos

    RISC-V Vector Core Team

  • ASIC Engineer at SpaceX
    Jun 2023 - Dec 2024 · 1 yr 7 mos

    • Primary responsibility was the performance verification of the SOC architecture which included feature rich ARM IPs, Interconnects, and DDR subsystems. • Lead the development of the performance test platform, which utilized Cadence emulation capable VIPs and System Performance Analysis (SPA). Performance analysis included cache and memory access patterns, IP QOS tuning, and interface (AXI, CHI) bandwidth profiling. • Designed a CPU model using System-C and TLM2.0 which was integrated within the SOC level UVM test bench as an UVC. The model replaces CPU RTL to simulate running C++ code, with significant simulation time speed up and improved debuggability. • Brought-up bare-metal ARM GCC-toolchain for bare-metal tests on CPU RTL for SOC team. Setup pre-run test GCC compile flow, back-door loading, and Arm Tarmac logging.

  • Digital IC Design Verification at MaxLinear
    Jun 2022 - Mar 2023 · 10 mos

    • Built and maintained UVM and System-Verilog testbenches for CPU subsystem. • Converted JTAG testbench from Xtensa LX4-CPU to LX7-CPU programming protocols. • Maintained Perl tool wrapper scripts for Cadence Xcellium, VManager, automated regression testing, and project management

  • Robotics Instructor at Robolink
    Oct 2018 - Sep 2020 · 2 yrs

    • Teaching students programming fundamentals in C++. • Coaching students from grades 4-8 to design, build and program robots to compete in the Vex IQ platform.

  • Software Engineering Intern at ASR Microelectronics International
    Jun 2019 - Sep 2019 · 4 mos

    • Improved the testing accuracy of cellular data, network, and WiFi stress tests by 98% and reduced testing times by 40%. • Used Tensorflow and Tensorflow Lite to develop an object detection neural model that could efficiently and accurately detect the location of signal icons. • Deployed model and maintained network stress tests in the Android testing app. • Assisted in the development of a smartphone testing management web tool, using Vue, Django, and RabbitMQ