Morgan Hill, California, United States
- Building world class flows to achieve power efficiency for sub-10nm designs in both HPC and low power classes of designs. Examples are AR/VR (Hololens), Gaming (XBOX) etc. - End to end experience as power lead in power estimation, modeling, optimization and silicon validation for a high-performance SoC design - Experience with defining, implementing and validating thermal management micro-architectures - Proponent of DFP methodology (DFP culture) with metric-based PPA closure. - Demonstrated expertise in power verification with UPF-based flows
Power management design and analysis of 16FF Holographic Processing Unit, pioneering advanced ASIC flow concepts Improving designer productivity across RTL design, RTL compilation, power analysis, and low power design and validation.
- Revamped the product strategy with a data-driven approach to engagements and customer successes - # of customer engagements grew manifold with a new product introduction - Improved product perception from a distant third to a close second by relentless emphasis on customer obsession.
- Successfully drove the transition from Einstimer to PrimeTime which boosted the EDA tool savings and enabled AMD to standardize on a single-vendor flow - PD team augmentation for several vital projects which resulted in on-time tapeout of advanced chips. - Expertise in low power helped to implement a power gating scheme for the interface block. This met or exceeded the power targets.