Boise, Idaho, United States
Specialties: Product Development Engineering of High Bandwidth Memory (HBM) DRAM and High-Density NAND Memory Devices. Integration of Design, Fabrication, Test and System Applications in product development. Academia Background: Integrated Temperature Sensor for Multi-Core SoC's, VLSI Analog & Mixed Signal Design.
Research, prototyping and future roadmap enablement for HBM production. 1. Develop, implement or incubate solutions space for new, unique, different and difficult issues to improve development cycle time. 2. Capture lessons learnt and ensure actionable commitments to improve forecasting accuracy and enhance practical quality coverage through effective DFT solutions. 3. Identify non-revenue generating overhead and pursue optimization vectors to be more efficient from pre-silicon to post silicon production.
Global Ownership of NAND Silicon Design for Test (DFT), Innovation Integration Technology. Engagement in NAND Product Pathfinding and Array Scaling.
Global Ownership of NAND Silicon Design for Test (DFT) and Advanced NAND Technology Pathfinding
Laboratory Instructor and Grader for EE330 Integrated Electronics and EE435 Analog VLSI Design
Research on Integrated Temperature Sensor for Multi-Core Systems on Chip
Develop test solutions in C for Automated Testing Equipment (ATE) to verify product specifications. Troubleshoot production issues and provide engineering support to test sites.