Adrian Bürli

R&D Director | Digital IC & SoC | Next-Generation Silicon Innovation for Business Impact

Vienna, Vienna, Austria

About

• Strong foundation in semiconductor technology from ETH Zürich • 18 years of experience in digital IC and semiconductor design • Lead architect for highly complex systems spanning ICs/ASICs, FPGAs, MCUs, IPs, GPU clusters, and embedded/software platforms Highlights: ‣ Multi-Tbit/s low-power data-path – from GPU-cluster to ASIC ‣ Multi-gigabit SerDes IP integration ‣ Time synchronization protocol achieving system-wide synchronicity down to nanoseconds ‣ Parallel sorting algorithm in silicon ‣ Circuit-level algorithm implementation ‣ Full-reticle digital IC design, CMOS circuits on thin post-processed membrane ‣ Python software for custom-routing in ultra power-optimized areas ‣ Large on-chip memory with built-in self-test • Deep expertise in RTL-to-GDS flows, SystemVerilog, hardware-software co-design, verification, IP development and integration, testing, embedded systems, software development, and electronics • Proven track record improving design methodologies, verification flows, design robustness, and release quality • Effective technical leader and mentor with strong cross-functional collaboration and communication skills

Experience

  • IMS Nanofabrication (18 yrs 8 mos)
    • Senior Director Electronics & MEMS
      May 2024 - Present · 2 yrs 2 mos

      • Director of department “Electronics and MEMS R&D” (2 management levels, 44 heads) • Technical responsibility over all department projects ‣ Technical review of digital IC design, FGPA firmware, embedded system design ‣ Review of development of MEMS post-process (Micro Electro-Mechanical System), and subsystem assembly

    • Technical Lead Digital ASIC Development
      Apr 2019 - Apr 2024 · 5 yrs 1 mo

      • Technical lead and architect for digital IC/ASIC designs (projects resourced with 5-8 engineers) • Architect, technical reviewer, mentor, hands-on implementer (SystemVerilog) • Rescued an inherited digital IC project by introducing a new architecture to achieve timing closure, tape-out in 28nm node • Introduced automated data exchange with design partners to shorten turn-around time and eliminate human errors

    • Director R&D Datapath and Control Systems
      Jun 2016 - Mar 2019 · 2 yrs 10 mos

      • Director of department “R&D Datapath and Control Systems” (1 management level, 35 heads) • Technical responsibility over all department projects ‣ Digital design (IC/FPGA/embedded systems) ‣ High-performance computing (HPC) ‣ Software development

  • Member of Scientific Staff at ETH Zurich
    Jun 2007 - Sep 2007 · 4 mos

    • MEMS integration of piezoelectric nano‑wires • Development and realization of a fabrication process (chemical vapor deposition, lift‑off) • Lab work, analysis using AFM and electron microscope imaging

  • Microelectronics Engineer, Internship Program at Intel
    Oct 2005 - Mar 2006 · 6 mos

    • Software development of EDA tools for low power digital design

  • Founder, Software Development at Berne Byte Bears GmbH
    1997 - 2002 · 5 yrs

    • Co‑Founder of software company; buyout in 2002 • Software development (web front‑/back‑end, databases, desktop applications)