Istanbul, Türkiye
Project experiences; 6. K2Semi Team lead, Determination of hardware architecture and implementation of LVDS interfaces. 5. Radar Target Simulator Team lead, Determination of hardware architecture. Implementation of echo signal generator and gigabit interfaces. 4. FOC Motor Control Projects Team lead, timing optimization(STA) and area(logic, DSP) optimization. 3. KIRMIK SoC H.264 Encoder and Decoder integration of ASIC tape out. Timing optimization(STA) and area(logic, memory) optimization. 2. Satcom Implementation of GSE(Generic Stream Encapsulation) algorithm on FPGA for SATCOM systems 1. H.264 Video Codec IP(*PROJECT section for detailed*) Baseline Encoder level 4.0 design and FPGA implementation. Baseline Decoder level 4.0 design and FPGA implementation. Interface and protocol experiences; Camera and Display IFs; Camlink ITU-R BT.656 DVP HDMI VGA External Memory; DDR2/3/4 M2 SSD SDRAM SRAM Bus Experiences; Avalon-MM Avalon-ST AXI4(Memory Mapped) AXI-Stream AXI-Lite APB Wishbone Data Communication IFs; PCIe (Root Complex, Endpoint) Ethernet Arinc429 UART I2C SPI Protocols; NVMe sFPDP Aurora UDP TCP
Hardware design for ASIC/FPGA with both VHDL and Verilog. High frequency architectural design Low area utilization architectural design Created scripts for simulation environments Performed functional verification and timing analysis of developed RTL Improving designs on area(logic, memory, dsp) and frequency(STA) issues.