Adelina Phạm

Silicon @ AMD

Ottawa, Ontario, Canada

About

Experience

  • Silicon Design Engineer 2 at AMD
    Jun 2025 - Present · 1 yr 2 mos

    SecIP Group

  • ASIC Digital Design Engineering Intern at Synopsys Inc
    May 2024 - May 2025 · 1 yr 1 mo

    1-year internship with Solutions Group for 224G SerDes Ethernet PHY IP

  • Teaching Assistant at Carleton University
    Sep 2024 - Dec 2024 · 4 mos

    Teaching Assistant for the third-year undergraduate course ELEC 3500: Digital Electronics The objective of this course is to introduce students to design of CMOS logic gates, digital circuit design using Verilog HDL and logic synthesis, asynchronous to synchronous interfacing, clock distribution and timing issues, digital circuit implementation and verification, digital memory and signaling technologies.

  • Electronics Intern at Ansys
    Jan 2024 - Apr 2024 · 4 mos

    QA with the Electronics Business Unit team for Ansys Electronics (HFSS) product

  • Hardware Design Intern at Ciena
    Sep 2023 - Dec 2023 · 4 mos

    With Packet-Optical 6500 team in: - Hardware verification, validation, qualification and debug - Signal integrity and reliability