India
Design Verification Engineer with 5+ years of experience, currently at Synopsys working on HBM Verification IP Development. Previously at Cadence Design Systems, verifying Xcelium tool features and performance. Worked as a Design Verification Engineer at Ceremorphic, Inc. on the LPDDR5 Memory Controller project. Worked as a Digital Design Engineer at SignOff Semiconductors, covering both RTL design and functional verification within the ASIC design flow. M.Tech in VLSI from Delhi Technological University (Formerly DCE). Skilled in: Digital Electronics, Verilog, SystemVerilog, UVM, Code Coverage, Functional Coverage, SystemVerilog Assertions, Feature Extraction from Specifications, Python Scripting, Lint Checking, Logic Synthesis, Gate-Level Simulation Protocols: AXI, APB, LPDDR, DFI, HBM, I2C Tools: Synopsys – VCS, Verdi Cadence – Xcelium, Genus Mentor – QuestaSim Xilinx – Vivado
Verification of new features and performance on customer design for Xceilium tool.
In-house project - •Did functional verification of I2C controller along with GLS. •Designed and verified lint free configurable GPIO with interrupts. •Generated python script for regression and UVM Testbench skeleton. Client Project - Siemens EDA: For ARM Kochab project, worked on top level verification plan documentation part