Barcelona, Catalonia, Spain
As a Certified VLSI Physical Design Engineer, I have developed work ethic that has allowed me to stay in touch with the latest innovations in Semiconductor field (Automotive, Mobile sectors ) while staying grounded in the basics of my profession. The Master qualification and ~7 years of Industry Experience has provided me to gain high technical training and understanding in VLSI field as Physical Design Engineer. I have developed my skills and knowledge in Synopsys ICC2, RTLtoGDSII, TCL and Signoff in different technology nodes like 28nm, 14nm, 10nm and 7nm. I have worked on High Frequency based block level designs, Latch based timing analysis, Place and Route, CTS, Floorplanning, ECO work, Low power designs, Mixed Signal Designs, Formal Verification, Physical Verification and TCL Scripting. With my current professional experience, I have matured my interpersonal, presentation and mentorship skills dealing with different colleagues, clients and developing relationship with them. In Addition to my experience and personal skills, I have a solid educational foundation and great interest in Semiconductor and embedded engineering. I have a understanding in how to increase the reputation by gaining an in-depth of project value and core concerns. I also have superior communication, leadership, team collaboration and time management skills to build consensus across relevant parties and drive business success.
Responsibilities: - TopLevel SoC PnR (Floorplanning to Route) for Automotive Radar Project in Mixed Signal Design in 28nm Technology - Responsible for Timing Analysis in Innovus - Script updates based on the PnR flow Tools used: Cadence Innovus
-- Qualcomm Client (FEB 2022 - ) Project 4nm Working on Floorplanning and PnR flow for Multi-Voltage based design. -- Signoff checks: Physical Verification, FV/Conformal Low Power, and Power Grid checks. Training: 2 months Training provided to graduate employees and Interns on PnR concepts and TCL commands in ICC2 compiler. -- Took Interviews of Interns and 1+ years experience professionals. CHALLENGES AND LEARNING • Floorplanning: Hands on Experience on Innovus; Memory Placement; PG Continuity and DRCs • Placement: Congestion, ISO cell Bounds, Legality, PG shorts, DRCs, • CTS: Long clock Nets; Clock Skew and High latency; Clock Tree Structure • Timing: DRCs (max cap, Max trans) ; Setup and Hold ; reg2reg paths • Signoff Challenges: PG Shorts, DRCs, Secondary PG Routing; CLP vios; LUP Vios; Bad NDR Routing • ECO: Timing Fixes; Manual Fixing; DRCs • Scripting : TCL scripting for easiness; Python Practicing
-- Trainings provided in ICC2 and PnR flow to new Joiners/1+ year experience -- Interviews taken of Undergraduate/1+ years experience -- Started Working on Client Location - Qualcomm
• Experienced in advanced technology nodes: 14nm, 10nm and 7nm projects. • Physical Design Knowledge from netlist to GDS-II tapeout including Floorplanning, Place and Route, Clock tree synthesis, timing closure and physical Verification. • Worked on High performance CPU partition closure. • Experienced on Latch based timing analysis and closure. • Experienced in Low power designs and closure of Timing critical and Routing Congested designs. • Expert in Synopsys ICC2 based flow to drive block PnR, Timing closure and Sign off. • Worked on Multiple projects/Blocks (15) in fixing ECOs with good hands in TCL commands & Sed/Awk and debugging to maintain the quality and timing criteria of the design. • Mentoring Interns/New employees and guiding them to understand the design flows and debugging. Learning Desire and Fearless attitude to accept any major challenges