Abhishek Maheshwari

SW Dev @ Meta | Ex-Intel | M.Tech CSE – IIT Kanpur | Kerne/Driver Dev | SmartNIC • Offload (Crypto, Compression) • RDMA | Enabled Google’s Falcon on Intel IPU | Firmware • SPDK Storage Virtualization | AI/HPC Enthusiast

Greater Bengaluru Area

About

Interested in fields of Machine Learning and Computer Vision

Experience

  • Software Engineer at Meta
    Sep 2025 - Present · 11 mos

  • MTS Software Development Engineer at AMD
    Jun 2025 - Aug 2025 · 3 mos

  • Intel Corporation (6 yrs 11 mos)
    • Cloud Software Development Engineer
      Aug 2021 - May 2025 · 3 yrs 10 mos

      Falcon Reliable Transport Protocol for RDMA • Google’s Swift as Datacenter Congestion control algorithm in HW and SW. • Owned platform Kernel driver and HW Manager user-space component managing device interrupts and resources. • Led the very first end-to-end RDMA-over-falcon bringup from Intel and debugged core functionality/datapath issues. Developed gRPC-based controlpath for Congestion Control configuration, Python debug tools and connection management. Virtio-blk Emulation for Mount Evans 200G IPU • Led design and development of the IPU Virtio-blk transport plugin in the opensource storage framework: SPDK. Enabled IPDK & OPI integration. • Exceeded customer requirements for storage datapath performance. Smart EndPoint for Mount Morgan 400G IPU • Jointly developed a Vfio-based user-space library driving PCIe Config-space and MMIO BAR emulation • Developed abstract transport library for HW mailbox communication

    • Network Software Engineer
      Jul 2018 - Dec 2021 · 3 yrs 6 mos

      QAT: QuickAssist Technology • Developed DMA firmware for next-generation QAT in IPU, code-store optimizations & performance enhancements. • Implemented Zstd Decompression & Snappy Compression Firmware. • Led multiple control path kernel driver features: interrupt enablement, PCIe PF/VF resource allocation, and reset flow via transport mailbox. • Collaborated on SDK, drove benchmarking, and system-level performance optimizations. FPGA based SmartNIC (for a leading PRC CSP provider) • Control plane SW, driving resource/queue mapping between host and SoC • SPDK-based app to intercept packets for handling sideband info from/to HW

  • Trainee Decision Scientist at Mu Sigma Inc.
    Jun 2015 - Oct 2015 · 5 mos

    ◆ Worked on demand estimation for UK's largest Catalogue retailer ◆ Collaborated in design & implementation of the demand estimation algorithm ◆ Contribution: Reduced runtime of the algorithm significantly by query optimization ◆ Technologies used: Hadoop, SAS, R, MySQL