Lowell, Massachusetts, United States
I write communications hardware for FPGA and data analysis tools in Python. I recently started a blog which you can read here: https://azimuthtech.wordpress.com/
FPGA and ASIC tooling.
Architect of Python data analysis tools for electronics characterization and industrial communications. Designer of VHDL hardware for test engineering projects. Author of novel knowledge-transfer-optimized documentation format. Author of reverse engineering and hardware/firmware formal verification training materials.
Hybrid one-on-one tutoring in C, operating systems, Python, Java, and advanced physics topics.
SERESL is part of the multi-university iTrace project, which studies how developers write and comprehend code using eye tracking technology. I added support for SmartEye brand eye tracking components and wrote XML sanitizing tools for legacy data.
Analyze and overhaul firmware for legacy products. Modified C++ firmware to support new GPS module with different electrical interface with minimal PCB impact. Identified and correct bugs associated with real time operating system and interrupt-driven measurement routines. Performed reverse engineering and documentation for in-house legacy test engineering tool.